Means for frequency/digital conversion

ABSTRACT

An arrangement for frequency/digital conversion, particularly for digital revolution and speed measuring, includes a clock unit, a control unit, and a counter unit. The clock unit provides a pulse train with a constant frequency. A multiplying unit is provided which gives a second pulse train, the frequency of which is dependent on the product of the constant frequency and the latest maximum value of the contents of the counter unit. The contents of the counter unit are reduced by a first quantity upon each pulse of the second pulse train. Another unit is arranged to supply the control unit with a third pulse train with an unknown frequency. The control unit emits a control signal to the counter unit for each pulse in the third pulse train. The counter unit increases its contents by a second quantity at the occurrence of such control signal. The second quantity is greater than or equal to the first quantity. After each such addition, the contents of the counter unit reach a new maximum value which constitutes a digital representation of the frequency of the second pulse train.

Valis Dec. 23, 1975 MEANS FOR FREQUENCY/DIGITAL CONVERSION lnventor: Jaroslav Valis, Vasteras, Sweden Assignee: Allmanna Svenska Elektriska Aktiebolaget, Vasteras, Sweden Filed: on. 7, 1974 Appl. No.: 512,624

Foreign Application Priority Data Nov. 22, 1973 Sweden 7315792 US. Cl 324/78 D; 307/220; 307/221; 307/225 Int. Cl. G01R 23/02 Field of Search 324/78 D; 307/220, 221, 307/225 References Cited UNITED STATES PATENTS 4/1974 Harris 324/78 D 4/1974 Russell et al... 324/78 D 10/1974 Terbrack 324/78 D COUNTER UNIT PICK-UP U/V/T Primary Examiner-John Kominski ABSIRACT An arrangement for frequency/digital conversion, particularly for digital revolution and speed measuring, includes a clock unit, a control unit, and a counter unit. The clock unit provides a pulse train with a constant frequency. A multiplying unit is provided which gives a second pulse train, the frequency of which is dependent on the product of the constant frequency and the latest maximum value of the contents of the counter unit. The contents of the counter unit are reduced by a first quantity upon each pulse of the second pulse train. Another unit is arranged to supply the control unit with a third pulse train with an unknown frequency. The control unit emits a control signal to the counter unit for each pulse in the third pulse train. The counter unit increases its contents by a second quantity at the occurrence of such control signal. The

second quantity is greater than or equal to the first quantity. After each such addition, the contents of the counter unit reach a new maximum value which constitutes a digital representation of the frequency of the second pulse train.

5 Claims, 4 Drawing Figures fly US. Patent Dec. 23, 1975 Sheet 2 of3 3,928,798

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3:4 1:4 I4 I4 t4t4 I4 mum BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a means for frequency/digital conversion.

2. The Prior Art Digital angular velocity speed measuring is usually carried out by methods which are based on speedlfrequency conversion by means of a pulse emitter mounted on, for example, an engine shaft, said pulse emitter generating a certain number of pulses per revolution, the output frequency being proportional to the number of revolutions per time unit. The frequency is then converted into numbers which are represented by a certain content in a counter. After counting, the contents of the counter unit are a direct measure of the speed.

A method like this involves a high resolution, accuracy of measurement, a high time and temperature stability due to a crystal-controlled time basis.

In order to obtaina resolution of, e.g., 0.1 by means of such a method, 10,000 measuring pulses must be counted at full speed. If the pulse emitter gives kHz at this speed, the time of counting will be 1 second.

For control purposes this measuring speed is insufficient since a step change of the measuring frequency in the worst case is not-indicated until after two measuring periods, i.e., after 2 seconds. For control purposes a time of counting which amounts to about milliseconds is an often required time of counting. A speed indication which is performed according to the method described above must be complemented with a DC tachogenerator equipment for such applications, which makes the method complicated and expensive.

SUMMARY OF THE INVENTION By means of a device for frequency/digital conversion according to the invention a speed indication can be performed with the desired speed at the high resolution desired by using an ingenious combination of available standard components.

The invention comprises an arrangement for frequency-digital conversion, particularly for digital revolution and speed measuring, the arrangement including a clock unit, a control unit, and a counter unit. The clock unit includes means to provide a pulse train with a constant frequency. A multiplying unit includes means to provide a second pulse train, the frequency of which is dependent on the product of the constant frequency and the latest maximum value of the contents of the counter unit. Means are provided to reduce the contents of the counter unit by a first quantity in response to each pulse of the second pulse train. Means are also provided to supply the control unit with a third pulse train with an unknown frequency. The control unit emits a control signal to the counter unit for each pulse in the third pulse train. The counter unit contents are increased by a second quantity at the occurrence of such control signal, the second quantity being greater than or equal to the first quantity. After each such addition, the contents of the counter unit reach a new maximum value which constitutes a digital representation of the frequency of the second pulse train.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described more fully with reference to the accompanying drawings, in which FIG. 1 shows the principle of a device according to the invention,

FIG. 2 an embodiment of the principle shown in FIG. A

FIG. 3 the connection between signals derived from the embodiment according to FIG. 2, and

FIG. 4 in graphic representation the result of a case study to which the means according to the invention has been applied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the embodiment shown in FIG. 1, the means according to the invention consists of a clock unit CLC arranged to deliver a pulse train CP with a specified clock frequency f,,, a synchronization and control unit SCL to which an -unknown pulse train FX with the frequency f is supplied from a pick-up unit PU and into which the pulse train CP from the the clock unit CLC is fed, a counter unit UDC to which there is fed a first control signal N from the synchronization and control unit SCL, a register unit RL which is connected to the counter unit UDC with a plurality of connections for transmitting the contents G in the counter unit UDC, and which may be influenced by the synchronization and control unit SCL by means of a second control signal LATCH, and a digital frequencymultiplying unit DRM into which the pulse train CP from the clock unit CLC and the contents F in the register unit RL are fed by means of several connections, the digital frequency-multiplying unit DRM emitting a pulse train FR arranged to influence the contents of the counter unit UDC with a third control signal N by way of the synchronization and control unit SCL.

First of all a theoretical description of the operation will be given in connection with FIG. 1, and then follows a detailed description of the operation in connection with FIG. 2.

The output signal from the multiplying unit DRM, i.e., the pulse train FR, the frequency of which f is proportional to the product of the frequency f of the pulse train CP delivered from the clock unit CLC and the contents F of the register unit RL according to the formula where l/M is a proportionality constant and where the counter unit UDC are reduced by N units. After each pulse in the unknown pulse train FX with the frequency f the synchronization and control unit SCL first generates a control signal N to the counter un'it UDC, after which its contents G are increased by N units, and thereafter a second control signal LATCH to the register unit RL, the contents G in the counter unit UDC being transmitted to the register unit RL. The synchronization and control unit SCL then controls the times of said subtraction and addition so that these do not coincide. Addition of N units and transmission of the contents G thus take place between two pulses in the contents of the counter unit UDC decrease gradually (when N l) by f T in total and are then increased by N If the contents of the register unit RL at the beginning of the k'th period of the unknown frequency f} are designated F the following applies:

Now, if the equations (1) and (2) are put together the following is obtained lff is constant and then F converges from the equation (3) towards F according to F=lim F 5) i.e., the contents F of the register unit RL are proportional to the unknown frequency f Furthermore, if

fc fr M l 0, i.e. if

i.e., if

the convergence is monotonous.

An alteration A F of F from the equation 2) during the kzth period of the frequency f results in fx M (7) This alteration AF, takes place during the period T For T 0, i.e.,

is obtained, and the dynamic behaviour of the means according to the invention can be approximately described by the differential equation dF =fv-r F which has a solution L, M-N M F(r)= fc 2 fY (l-e) 9 and for t-w the following is obtained The quotient according to the equation (9) corresponds to the inverse value of the time constant of the exponential function, namely It can be noted in this context that F, i.e., the contents of the register unit RL, for high frequencies converges exponentially towards From the equations (ll) and (6) the following is obtained i.e., the time constant TM is equal to the period T for the lowest measuring frequency giving monotonous convergence. I

The convergence process in case of lower frequencies deviates from the exponential process the more f approaches f However, a correct measuring value is obtained as quickly as in the case of high frequencies, i.e., during a time corresponding to 3 to 5 times 1 For a practical case illustrated in FIG. 4 a resolution of F is obtained with 0.10 0, nr-i 10 msec, lowest measuring frequency for monotonous convergence fxmi" Hz, lowest measuring frequency for stable convergence f 50 Hz, where maximum measur- FIG. 2 shows a specific embodiment of the arrangement according to FIG. 1.

The clock unit CLC comprises a crystal-controlled oscillator OSC and a number of inverters 1N IN and IN, with additional elements R R and C. The inverter IN and the inverter IN included in the synchronization and control unit SCL amplify and convert the output signal from LI oscillator into a square-shaped pulse train CP and CP, respectively. See FIG. 3 which describes the time relations between the pulse trains mentioned below.

The digital frequency multiplication DRM consists of four cascade-connected multiplication elements DRMO, DRMl, DRM2 and DRM3 and a NAND gate A The cascade connection is brought about by the connection between the ENABLE INPUTS and EN- ABLE OUTPUTS, respectively, of the respective multiplication elements.

Each multiplication unit is supplied to the pulse train CP and is connected, by way of its inputs A, B, C and D, to the respective inputs Q Q Q and Q of the 4-bit register elements RLO, RLl, RL2 and RL3 of the register unit RL. Each multiplication unit DRMO, DRMl, DRM2 and DRM3 generates a pulse train F F F and F respectively, the average frequencies of which are OUT2 2 fc fOUTO 0 0-0001 f0 where F F F and F are the contents (preferably in BCD code) of the respective register elements RLO, RLl, RL2 and RL3 and f the frequency of the pulse train CP.

Negative output signals F F F and F are added by means of the NAND gate A into a pulse train FR, the average frequencies of which are f =f 'fourz +f0urr 'fouro fc a 2 0001 1 00001 F The counter unit UDC consists of four reversible counter elements UDCO, UDCl, UDC2 and UDC3.

Each counter element has separate inputs for counting up and counting down, here UP and DOWN, respectively. A change in the condition of one counter element upwards or downwards is made at the positivegoing edge of the respective input signal to UP or DOWN whereas the signnal on the second of UP or DOWN is high (logical one).

When counting up (down) a counting pulse is passed to the CARRY (BORROW) output when the state of the counter element is changed from 9 to 0 (0 to 9). This means that the counter elements can be cascadeconnected by connecting a CARRY (BORROW) output to an UP (DOWN) input of the next counter element. The current state of each counter element is available on its Q Q 0 and Q -outputs which are connected to A-, B-, C- and D-inputs, respectively, of one register element each in the register unit RL.

According to the connection in FIG. 2 all counter elements UDCO UDC3 are cascade-connected for counting down I pulses on the DOWN input of the counter element UDCO. The UP input of UDCO is connected to a high logical level H. Only the counter elements UDC2 and UDC3 are cascade-connected for counting up a pulse on the UP input of the counter element UDC2, which means that each counting down by 1 unit of the counter element UDCO reduces the contents of the entire counter unit UDC by 1, whereas each signal N increases the contents of the entire counter by units.

The synchronization and control unit SCL consists of four flip-flops FFl, FF2, FF3 and FF4, a number of inverters 1N IN IN IL [L 1L [L [L and [L and NAND gates A A A A and A For each negative-going edge of the pulse train CP (i.e., for each positivegoing positive-going of the pulse train CP) the output Q of the flip-flop FF3 is set to one, and its output signal DCP becomes high, i.e., a logical one. The signal DCP is delayed in inverters IL IL and IN; to the signal S1 which sets the flip-flop FF3, and thus also the signal DCP, to zero by way of the CLEAR input of the flip-flop FF3.

Accordingly, DCP becomes a positive pulse with a determined pulse length.

Through the NAND gate A an inverted logical prodnet is formed by the signal DCP, the output signal FR from the multiplication unit DRM and the signal DCE. (As regards DCE, see below.)

If the signal DCE is high and a pulse has been generated in the pulse train FR while a clock pulse period T is in progress, a signal is obtained on the output of the NAND gate A giving a negative pulse of the same length as the pulse of the signal DCP and reducing the contents of the counter unit UDC by 1 unit. If no pulse has been generated in the signal FR, the output signal from the NAND gate A remains high and no subtractions are performed.

The subtraction as above is repeated as long as the contents of the counter unit UDC are positive. When the contents of the counter unit UDC become negative, i.e., 9999, a negative pulse is obtained on the BOR- ROW output of the counter element UDC3, and the NAND gates A and A, which are connected and operate as a flip-flop change the state of the output signal DCE and a further. counting down of the counter unit UDC is stopped.

The signal FX, the frequency f of which is to be converted, is presupposed to be converted into a pulse train with logical levels according to TTL logic.

When the signal FX is low the flip-flops FFl, FF 2 and FF3 are set to zero, i.e., the signal N from the Q-output of the flip-flop FF2 is high and the signal LATCH from the Q-output of the flip-flop FF4 is low. When the signal FX becomes high the flip-flop FFl is set to one at the next positive-going edge of the signal S1, i.e., a certain time after the signal N, on the output from the NAND gate A has become high and a unit has been subtracted from the counter unit UDC.

A high signal S2 on the Q-output of the flip-flop FFl sets the flip-flop FF 2 to one, and the signal of said flip-flop FF2 on the 0- output, i.e., N becomes low. After a certain time the flip-flop FF2 is set to zero by the fact that the signal S4, which is the output signal for the Q-output of the flip-flop FF2 which has been inverted and delayed by the inverters 1L IL and IN becomes low.

The signal N is fed in at the UP-input of the counter element UDC2, the total contents of the counter ele- 7 ment UDC2 and UDC3 increasing by one unit and, consequently, the contents of the whole counter unit .UDC by 100. The signal N also affects the flip-flop A -A so that the signal DCE becomes high if this is not already the case.

The signal S4 is delayed in the inverters 1L and IL and in the NAND gates A and A to the signal S5, said NAND gates being connected as inverters. The positive-going edge of the signal S5 sets the flip-flop FF4 to one when its D-input is high. The time delay of the signal S4 is longer than the time required for the counter elements UDC2 and UDC3 to change their conditions after the addition of 100 units.

When the flip-flop FF4 is set to one and the signal LATCH is high, the contents of UDCO, UDCl, UDC2 and UDC3 are transferred to their respective register units RLO, RLl, RL2 and RL3, and the register unit RL will therefore contain a new measuring value. The flip-flop F F4 and the signal LATCH will thus change to low level when the next pulse train CP shows a positive-going edge.

From the last-mentioned pulse onwards the multiplying unit DRM generates a pulse train with an average frequency commensurate to the new contents F of the register unit RL.

When the signal FX becomes low the flip-flop is set to zero, and thus the procedure decribed above is ready for repetition when the signal FX becomes high next time at the beginning of a new period of the measuring frequency f As pick up unit PU it is possible to use, for example, an AIRPAX Zero Velocity Digital Pickup Model 4-0001. The four multiplication elements DRMO- DRM3 may, for example, consist of four Texas Instruments SN 74167.

The four register elements RLO-RL3 may, for example, consist of four Texas Instruments SN 7475.

The four counter elements UDCO-UDC3 may, for example, consist of four Texas Instruments SN 74192.

The four flip-flops FFl-FF4 may, for example, consist of two Texas Instruments SN 7474.

The two NAND gates A and A may, for example, consist of a Texas Instruments SN 7420.

The four NAND gates A A A and A may, for example, consist of a Texas Instruments SN 7400.

The six inverters II ,,IL may, for example, consist of a Texas Instruments SN 74L04 and the six inverters IN,-IN of a Texas Instruments SN 7404.

The crystal in the crystal-controlled oscillator OSC may be of the HC-6 type.

The counter unit UDC and the multiplication unit DRM can also be adapted to operate with another code than the BCD shown here by replacing the respective rect current tachogenerators in position servo systems with digital increment and absolute position measuring or with step motors.

An arrangement according to the invention also makes possible a quick an accurate measuring of very low frequencies. For a measuring range of 001-1 Hz and a resolution of 0.01 for example, a time of measuring of only seconds is obtained with the means according to the invention, whereas conventional pulse counting would require 2.8 hours.

The arrangement according to the invention is of course not limited to the embodiment shown here, but can be varied in many wayswithin the scope of the following claims.

I claim:

1. Apparatus from frequency/digital conversion, especially for digital revolution and speed measuring, which comprises a clock unit (CLC), a control unit (SCL), and a counter unit (UDC), the clock unit (CLC) including means to deliver a first pulse train (C?) with a constant frequency (f,;), in which the apparatus comprises a multiplying unit (DRM) including means to deliver to the control unit a second pulse train (FR), the frequency of which (f,,) is dependent on the product of said constant frequency (f and the latest maximum value (F) of the contents (G) of the counter unit (UDC),

the counter unit (UDC) including means to reduce its contents (G) by a first quantity (N in response to each pulse in the second pulse train (FR), another unit (PU) including means to supply the control unit (SCL) with a third pulse train (FX) with an unknown frequency (f the control unit (SCL) including means to emit a control signal to the counter unit (UDC) for each pulse in the third pulse train, the counter unit (UDC) increasing its contents (G) by a second quantity (N at the occurrence of said control signal, said second quantity (N being greater than or equal to said first quantity (N and after each such addition the contents (G) of the counter unit (UDC) having reached a new maximum value (F) which constitutes a digital representation of the frequency (f of the second pulse train (FX).

2. Apparatus according to claim 1, in which ,the frequency 0);) of the second pulse train (FR) is equal to the product of said constant frequency (f and said maximum value (F) divided by a proportionality constant (M) which is greater than said maximum value (F).

3. Apparatus according to claim 1, which comprises a register unit (RL) connected between and to the counter unit (UDC) and the multiplying unit (DRM), said register unit including means to memorize a first maximum value (F of the contents (G) in the counter unit (UDC) until a second maximum value (F has been obtained.

4. Apparatus according to claim 1, in which the ratio between said first quantity (NJ and said second quantity (N is 10', p being an integer.

5. Apparatus according to claim 1, in which the ratio between said first quantity (N and said second quantity (N is 16", q being an integer. 

1. Apparatus from frequency/digital conversion, especially for digital revolution and speed measuring, which comprises a clock unit (CLC), a control unit (SCL), and a counter unit (UDC), the clock unit (CLC) including means to deliver a first pulse train (CP) with a constant frequency (fC), in which the apparatus comprises a multiplying unit (DRM) including means to deliver to the control unit a second pulse train (FR), the frequency of which (fR) is dependent on the product of said constant frequency (fC) and the latest maximum value (F) of the contents (G) of the counter unit (UDC), the counter unit (UDC) including means to reduce its contents (G) by a first quantity (N1) in response to each pulse in the second pulse train (FR), another unit (PU) including means to supply the control unit (SCL) with a third pulse train (FX) with an unknown frequency (fX), the control unit (SCL) including means to emit a control signal to the counter unit (UDC) for each pulse in the third pulse train, the counter unit (UDC) increasing its contents (G) by a second quantity (N2) at the occurrence of said control signal, said second quantity (N2) being greater than or equal to said first quantity (N1), and after each such addition the contents (G) of the counter unit (UDC) having reached a new maximum value (F) which constitutes a digital representation of the frequency (fX) of the second pulse train (FX).
 2. Apparatus according to claim 1, in which the frequency (fR) of the second pulse train (FR) is equal to the product of said constant frequency (fC) and said maximum value (F) divided by a proportionality constant (M) which is greater than said maximum value (F).
 3. Apparatus according to claim 1, which comprises a register unit (RL) connected between and to the counter unit (UDC) and the multiplying unit (DRM), said register unit including means to memorize a first maximum value (Fk) of the contents (G) in the counter unit (UDC) until a second maximum value (Fk 1) has been obtained.
 4. Apparatus according to claim 1, in which the ratio between said first quantity (N1) and said second quantity (N2) is 10p, p being an integer.
 5. Apparatus according to claim 1, in which the ratio between said first quantity (N1) and said second quantity (N2) is 16q, q being an integer. 